Board Configuration
4
Board Configuration
Some SPT711xPFCE features are not enabled when the board is shipped from the factory. Carefully
evaluate the features and their conflicts before enabling them.
4.1
Reset and Boot Mode Selection
The complex programmable logic device (CPLD) controls reset and boot mode selection. It contains the
logic necessary to assert PORESET to all four MSC711x devices and individual HRESET to each
MSC711x device. The host can also change the boot mode selection signals to all four MSC711x devices.
By default, all devices reset to boot mode 0b0000 with SWTE and DBREQ deasserted. For details, see
The on-board reset circuitry has been minimized and handles only initial powerup and final powerdown.
The circuitry requires a rise/fall time of at least 1 V per 25 ms for both external voltage sources. Also, the
external 5 VDC supply must begin rising within 100 ms of the time when the external 3.3 VDC source
reaches 2.90 VDC. The reset circuitry issues a PORESET when the external 3.3 VDC source drops below
2.95 VDC or when the 5 VDC source drops below 0.8 VDC. These requirements are reasonable for the
board’s intended use.
If the external 5 VDC supply is between 0.8 VDC and 3.0 VDC after 200 ms of the external 3.3 VDC
reaches 2.95 VDC, the core voltage may “brown out” without triggering a PORESET. The host processor
must issue a PORESET through the CPLD registers to reset the cores.
4.2
Optional Resistors
Several optional features can be enabled or disabled by installing and/or removing resistors, as detailed in
Table 5. Optional Resistors
R181 (R179)
R2 (R1)
R8 (R5)
R285 (R54)
R40 (R41)
R121 (R78)
R124 (R15)
R56 (R55)
R51 (R52)
U6 (R148, R135)
U3 (R150, R97)
U14 (R221, R244)
Resistor
Option
JTAG Chain Bypass CPLD
JTAG Chain Bypass SL0
JTAG Chain Bypass SL1
JTAG Chain Bypass SL2
JTAG Chain Bypass SL3
TPSEL = 0 SL0
TPSEL = 0 SL1
TPSEL = 0 SL2
TPSEL = 0 SL3
SPI EEPROM SL0
SPI EEPROM SL1
SPI EEPROM SL2
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
22
Freescale Semiconductor
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